1. Field of the Invention
This invention relates to digital interface design, and more particularly, to designing a ULPI (UTMI+ Low Pin Interface).
2. Description of the Related Art
Within the past two decades personal computers (PC) have joined television sets, high fidelity stereo equipment, and compact disc players as part of the vast array of electronic devices widely used in both the office and the home. The Universal Serial Bus (USB) was developed to offer PC users an enhanced and easy-to-use interface for connecting an incredibly diverse range of peripherals to their computers. The development of the USB was initially driven by considerations for laptop computers, which greatly benefit from a small profile peripheral connector. Among the many benefits of the USB is a reduction in the proliferation of cables that can affect even the smallest computer installations. In general, USB has become the interface of choice for PCs because it offers users simple connectivity. USB eliminates the need to have different connectors for printers, keyboards, mice, and other peripherals, and supports a wide variety of data types, from slow mouse inputs to digitized audio and compressed video. In addition, USB devices are hot pluggable, i.e. they can be connected to or disconnected from a PC without requiring the PC to be powered off.
The USB specification has seen various revisions, with the USB 2.0 standard challenging the IEEE 1394 interface (“Firewire”) as the interface of choice for high-speed digital video, among others. With the proliferating design of increasingly smarter, faster, and smaller peripherals, the On-The-Go (OTG) Supplement to the USB 2.0 Specification [Ref 2] was developed to address the growing popularity of the portable electronic devices market. Some of the advantages of the USB and OTG include the built-in support in form of more than 1.4 billion USB enabled PC's and peripherals shipped worldwide, smooth and trouble-free experience for the user through a compliance and logo program operated by the USB-IF, a wide variety of USB solutions such as intellectual property (IP) blocks, system-on-chip (SOC) parts, discrete chips, software drivers and systems offered by a large group of industry vendors, and design flexibility based on system needs.
OTG devices typically do not require a PC host, and can communicate directly with each other. For example, a PDA may act as a USB host with the capability to print directly to a USB printer, while also acting as a USB peripheral to communicate with a PC. In general, designers are facing increasing pressure to design smaller and faster products in less time and at lower cost. Concurrently, the introduction of smaller deep sub-micron processes present new challenges, such as integrating the physical layer (PHY—transceiver) analog circuitry required by technologies such as USB and OTG, leading to increased man-hours, fiscal and time investment, and silicon revisions. One way to increase time-to-market while keeping costs low is to provide the PHY in a separate chip. In such a case the designer can typically integrate most of the USB digital logic into the application specific integrated circuit (ASIC) in a small amount of time, and connect to a proven external PHY already available on the market.
Following the release of the USB 2.0 specification, Intel released the USB 2.0 Transceiver Macrocell Interface (UTMI) specification. UTMI defined an interface between two IP blocks: the USB Transceiver Macrocell (IP) and the USB Link layer (SIE). The signals for a UTMI interface with an 8-bit bi-directional data bus. Typically a minimum of 22 signals is required between the Link and the PHY for a device.
Subsequently, an extension of the original UTMI specification the UTMI+ specification was developed to meet the emerging need of building embedded host and OTG capabilities into USB devices. While the original UTMI specified an interface not meant to couple discrete ICs, the UTMI+ in essence introduced host and On-The-Go capabilities to USB systems. Using UTMI as a starting point, UTMI+ incrementally adds new functionality and interface signals to the Link and PHY. The additional signals total 33 for a full OTG UTMI+ interface. Designers can reuse all blocks from their original UTMI IP, and need only add the new circuits required for host or OTG support. This approach works well for UTMI+, as USB peripherals need only a subset of host and OTG functionality. UTMI+ introduced four levels of functionality, each higher level increasing the complexity required in both hardware and software while remaining completely backward compatible with lower levels.
More recently, a group of USB industry leaders developed a Low Pin Interface (LPI) UTMI+ specification, referred to as ULPI, in order to provide a low-cost USB and OTG PHYs by way of a low-pin, low-cost, small form-factor transceiver interface that may be used by any USB application. Pre-existing specifications, including UTMI and UTMI+ were developed primarily for Macrocell development, and were thus not optimized for use as an external PHY. Building upon the existing UTMI+ specification, the ULPI reduces the number of interface signals to 12 pins, with an optional implementation of 8 pins. As a result, the package size of PHY and Link IC's has generally been reduced, not only lowering the cost of Link and PHY IC's, but also reducing the required size of the associated printed circuit boards (PCBs). Central to the ULPI specification is the LPI, which is in effect a generic bus that defines a clock, three control signals, a bi-directional data bus, and bus arbitration. An introduction to ULPI has been published in March 2004.
Typically, a ULPI link will configure the ULPI PHY using register writes on a bi-directional shared data bus. The ULPI PHY is the arbitrator of the 8-bit data bus between the link and the PHY. As a result of certain events, for example a USB Linestate, OTG Vbus comparator, or IdDig plug, the PHY will typically assert the DIR signal and gain immediate access to the data bus. In such a situation, if a link write to the register array internal to the USB PHY is in progress, the data bus will not contain the data to write into the register array of the PHY. The ULPI specification does not directly describe this particular sequence of events, and offers no specific scenarios as to how this issue should be addressed. Generally, link vendors will build into their devices a way to detect the assertion of DIR and re-schedule another write to the ULPI PHY register. However, in the link re-scheduling a write, the correct data may not necessarily be written during the next write operation. In the USB protocol, unanticipated changes on DP/DM—caused by a write to the Function control register, for instance—may be misinterpreted on the other end of the USB bus leading to an unexpected state, which would interfere with proper operation of the USB devices on either end of the USB bus.
A ULPI link may also cause a register write operation that overlaps a USB receive event when the write cycle is terminated with the ULPI STP signal. In case the ULPI STP signal is asserted on the second cycle after the ULPI DIR is asserted, the ULPI PHY may interpret it to mean a LINK abort command. As a result of this action by the link, the incoming USB received packet may be lost and the link may be unaware that it has just aborted the PHY's USB receive. The STP signal is generally used as a means of ending the USB transmit. STP may be asserted once the complete transmit packet has been transferred into the ULPI PHY. An STP signal may also be used to end a ULPI register write. In debug mode, the STP signal may be used to abort a babbling USB device. This mode is typically not used in normal operation of the link and PHY. The ULPI 1.1 specification only requires that the PHY ignore an abort in the first cycle after a DIR signal has been asserted. In practice this may lead to unexpected register writes when in development. The link would have to combinatorially sample the state of the DIR signal before issuing an STP signal. Thus, the link would not issue the STP signal upon detecting the DIR signal. Without the STP signal the PHY would remain in the register write state waiting for the STP signal to be issued. However, requiring the link to sample the DIR signal would preclude the design of a clean synchronous interface to the PHY.
FIG. 1 shows a timing diagram of a ULPI register write operation. During normal operation the LINK drives a TXD CMD, in other words a register write on the bi-directional Data[7:0] bus at time T0. Bits 5:0 of this command byte contain the register address, which is the target of the register write command. Bit 7:6 of the command byte are decoded to determine if a USB Transmit, Register read, or Register write are to occur. At time T1 the ULPI PHY drives the NXT output, which the LINK detects at time T2, and then advances to drive the register data[n] byte. The LINK completes the write register transaction at time T3 when the STP is asserted. The ULPI PHY detects STP at time T4, and before the rising edge of the clock at time T5 the ULPI addressed register is updated.
Generally the ULPI PHY is the arbitrator of the bi-directional data bus. USB receive data typically has the highest priority. The ULPI PHY uses the DIR output to gain control of the data bus. This may result in a situation where an interrupt causes the ULPI PHY to report a status change via the RXD command byte to the LINK, or a USB receive occurs, causing USB data to be transferred to the LINK. A ULPI PHY may request the data bus due to one or more of the following changes:                LINESTATE change on USB BUS DP/DM        OTG Comparator Change due change in VBUS        ID pin state        Host Disconnect detection        USB Receive Start of Packet detection        
Any of the above conditions may occur at any time and may interrupt a register write operation already in progress. The ULPI specification contains specific information about how a register write may be interrupted. It does not unequivocally state however, how the PHY must behave with regards to the internal registers when a register write operation is interrupted.
FIG. 2 shows a timing diagram of an RXD command interrupting a register write operation. In other words, an RXD byte interrupt occurs when the LINK is writing to the internal register array. At time T1, the PHY asserts DIR to signal to the LINK that higher priority information is available. The bus turnaround cycle completes at time T2, and the PHY drives the RXD command byte. The LINK accepts the RXD command byte at clock edge T3. The PHY should not accept any write to the internal register array after the assertion of DIR. The LINK must re-try the write to the internal register array when DIR is de-asserted after time T4.
FIG. 3 shows a timing diagram of a ULPI register write immediately followed by a USB receive. In other words, a USB receive immediately follows a USB receive. Since the USB receive data is of higher priority than the register write, the ULPI PHY may assert DIR at time T3. The write in this case may complete since the STP signal asserts after time T3, and the PHY has already registered the register data at time T3. The USB receive starts at time T4 with an RXD command byte followed by the USB PID, which is received by the link at T5 followed by the remaining bytes of the packet.
FIG. 4 shows a timing diagram of a ULPI register write interrupted by a USB receive, where a USB receive occurs one cycle earlier than shown in FIG. 3. At time T2 the ULPI PHY asserts DIR due to a USB receive. The write register command is ignored since the data on the bus when STP is asserted is unknown. AT time T3 a ULPI bus turnaround cycle allows the PHY to drive the data bus after cycle T4.
Since the ULPI specification does not specifically describe how the PHY must behave with regards to the internal registers when a register write operation is interrupted, there exists a need for a system and method to protect the integrity of the internal registers during interrupted write operations.
Many other problems and disadvantages of the prior art will become apparent to one skilled in the art after comparing such prior art with the present invention as described herein.